This invention relates to single metallization complementary n-channel and p-channel field-effect transistor apparatus of the enhancement mode and periodic table group III-V material composition type.
Complementary pair transistors are found useful in both the discrete component and the integrated circuit embodiments of active electrical circuits. In the discrete component era of electronic circuits it was, for example, popular to dispose PNP and NPN bipolar transistors in the complementary pair configuration for driving components such as an electrical transmission line or an audio loudspeaker or a computer clock bus of relatively fast rise and fall time characteristics. More recently the silicon-embodied CMOS line of field-effect transistor integrated circuit devices has been used in these and other applications wherein substantial bidirectional current flow in a load is needed. Notably, however, the use of complementary pair transistors in the realm of gallium arsenide embodied semiconductor devices has been less frequent.
Some part of this lesser use is believed attributable to complexity and cost considerations attending the fabrication of gallium arsenide complementary pair devices and some part to the adequacy of Silicon fabricated devices in many circuit applications. For certain transistor applications, however, gallium arsenide devices of this complementary pair arrangement are needed. These applications include radio frequency circuits operating in the microwave and higher frequencies, especially in space vehicles where radiation resistance and low energy consumption are significant design considerations and also in other high speed amplifier circuits, e.g., in the presently active personal communications environment. The present invention is believed to present a simplified complementary pair arrangement which overcomes significant parts of the complexity and cost factors in this situation by, for example, reducing the number of mask levels needed for complementary pair fabrication from thirteen to seven and the number of process steps from nineteen to eleven when compared with silicon CMOS circuits. Moreover, when compared with gallium arsenide complementary heterostructure field-effect transistor (CHFET) devices this simplification yet comprises a reduction from fourteen process steps to eleven and ten mask steps and mask levels to seven.
The present invention therefore provides a transistor apparatus in which complementary p-channel and n-channel metal oxide semiconductor field-effect transistor devices of single metallization character are carried on a common substrate. The single metallization provides gate contact and the source/drain contacts in each of the transistors in a manner which is practical, economically viable and does not require separate masking steps for the Schottky barrier and ohmic junction contacts. The invention arises from compromise between several semiconductor device disciplines--including material growth, device metallization, and material deposition. The achieved complementary field-effect transistors are technically and economically viable for use in analog transistor applications extending to the microwave and millimeter wave spectral regions--especially in the low power, low energy, radiation incurring operating environments found in the space environment for example.
Several concepts appearing in the present invention also appear in the patent and publication literature as stand-alone concepts. Using the same metal in parts of the source, drain and gate structure of a field-effect transistor, for example, appears in a certain form in transistors fabricated some years ago when the self-aligned gate structure was new in the art. Examples of this same metal usage appear, for example, in the two related patents of Napoli et al., U.S. Pat. No. 3,764,865 and U.S. Pat. No. 3,861,024. Same metal usage also appears in the two related Westinghouse patents of Kim, U.S. Pat. No. 3,855,690 and U.S. Pat. No. 3,943,622.
In each of these four patents however, the disclosed transistor involves use of a common metal to connect to an already formed source/drain ohmic contact and to form the Schottky barrier gate contact. In the silicon material used in the devices of these four patents an ohmic contact is moreover achieved with the mere addition of another layer of material and does not require the alloying, annealing and other complexities often needed for a group III-V semiconductor device ohmic contact. The present invention is believed distinguished over the disclosure of these older patents by its use the same metal to actually form the gate contact as to form the source/drain contacts of the transistor. Moreover, in the present invention these source/drain contacts are achieved in a non-alloyed fashion in both the p-channel and n-channel devices of a complementary pair.
The U.S. Pat. No. 4,961,194 of S. Kuroda et al., describes gallium arsenide MESFET and HEMT devices which use the combination of non-alloyed ohmic contacts, same metal electrodes, acetone solvent removal of photoresist coatings and selective etching. Although several of these practices find use in the present invention, additional concepts not disclosed in the Kuroda et al. patent are also a part of the present invention and provide significant distinction. The Kuroda et al. patent, for example, does not disclose the use of a permanent secondary mask and passivation material layer nor a gate aperture recess received in a gate window. In view of the similar areas of work and in the interest of minimizing the size of the present patent document, however, the contents of the of S. Kuroda et al. U.S. Pat. No. 4,961,194 are hereby incorporated by reference herein.
An article published in the technical literature some years ago is also of interest with respect to the single metal concept and is additionally of interest with respect to the use of non-alloyed ohmic contacts in a field-effect transistor. This article "A New Fabrication Technology for AlGaAs/GaAs HEMT LSI's Using InGaAs Non-alloyed Ohmic Contacts" is authored by S. Kuroda et al., apparently the same S. Kuroda et al., as appears in the above identified U.S. Pat. No. 4,961,194, and appears at page 2196 in the Institute of Electrical and Electronic Engineers Transactions on Electron Devices, Volume 36, number 10, October, 1989. This Kuroda article is in fact of an especially enlightening contrast in nature with respect to the present invention since it teaches the use of a complex etching sequence during formation of certain elements and the present invention avoids use of such a sequence in favor of a more practical and less costly procedure.
In a somewhat related situation the technical article "All-Refractory GaAs FET Using Amorphous TiWSi.sub.x Source/Drain Metalization and Graded In.sub.x Ga.sub.1-x As Layers" authored by N. Papanicolaou which appears at page 7 in the Institute of Electrical and Electronic Engineers Electron Devices Letters, volume 15, number 1, January, 1994 discloses the use of non-alloyed ohmic contacts in a gallium arsenide field-effect transistor. The Papanicolaou article however, relates to the fabrication of a high temperature field-effect transistor device, a device having refractory metal elements and involving the use of Tungsten metal. The Papanicolaou article also presents an informative discussion of the non-alloyed ohmic contact art.
The inventors of the present invention have also found the textbook "Modern GaAs Processing Methods" authored by Ralph Williams, Artech House, of Boston and London, to be of assistance in explaining and understanding certain aspects attending the present invention including its relationship with the prior art. In the further interest of minimizing the size of the present patent document, the contents of the Ralph Williams, Artech House textbook are therefore hereby incorporated by reference herein.
Non-alloyed ohmic contacts and other features relating to the present invention are additionally disclosed in several technical articles as follows.
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Campbell, "Heavy Ion and Proton Analysis of a GaAs C-HIGFET SRAM", IEEE Trans. Nucl. Sci., vol. 40, pp. 1660-1665, 1993. PA1 [6] D. DiBitonto, W. Karpinski, K. Lubelsmeyer, D. Pandoulas, G. Pierschel, C. Rente, K. Subhani, and F. Tenbusch, "Radiation and Cryogenic Test Results with a Monolithic GaAs Preamplifier in C-HFET Technology", Nucl. Inst. Methods Phys. Res. A, vol. 350, pp. 530-537, 1994. PA1 [7] W. Karpinski, K. Lubelsmeyer, D. Pandoulas, G. Pierschel, C. Rente, K. Subhani, and F. Tenbusch, "Characteristics of GaAs Complementary Heterojunction FETs (C-HFETs) and C-HFET Based Amplifiers Exposed to High Neutron Fluences", Nucl. Inst. Methods Phys. Res. A, vol. 361, pp. 558-567, 1995. PA1 [8] R. Williams, Modern GaAs Processing Methods, 2nd ed., Artech House, Norwood, Mass., pp. 260-270, 1990. PA1 [9] M. Hagio, S. Katsu, M. Kazumura, and G. Kano, "A New Self-Align Technology for GaAsAnalog MMIC's", IEEE Trans. on Elect. Dev., vol. 33, no. 6, pp. 754-758, June 1986. PA1 [10] G. C. DeSalvo, T. K. Quach, R. W. Dettmer, K. Nakano, J. K. Gillespie, G. D. Via, J. L. Ebel, and C. K. Havasy, "Simplified Ohmic and Schottky Contact Formation for Field Effect Transistors Using the Single Layer Integrated Metal Field Effect Transistor", IEEE Trans. on Semi. Manufacturing, vol. 8, pp. 314-318, 1995. PA1 [11] C. K. Havasy, T. K. Quach, C. A. Bozada, G. C. DeSalvo, R. W. Dettmer, J. L. Ebel K. Nakano, J. K. Gillespie, and G. D. Via, "A Highly Manufacturable 0.2 .mu.m AlGaAs/InGaAs PHEMT Fabricated Using the Single-Layer Integrated-Metal FET (SLIMFET) Process", GaAs IC Symposium Proceedings, San Diego, Calif., Oct. 29-Nov. 1, 1995, IEEE Press, Piscataway, N.J., pp. 89-92, 1995. PA1 [12] H. Kaakani, "GaAs CHFET Overview", Personal communication between Phillips Laboratory, Kirtland, AFB, NM and Honeywell Solid State Electronics Center, Plymouth, Minn., February, 1995. PA1 [13] J. K. Abrokwah, J. H. Huang, W. Ooms, C. Shurboff, J. A. Hallmark, R. Lucero, J. Gilbert, B. Bernhardt, and G. Hansell, "A Manufacturable Complementary GaAs Process", 1993 IEEE GaAs IC Symposium Technical Digest, IEEE Press, Piscataway, N.J., pp. 127-130, 1993. PA1 [14] M. Meyer, "Digital GaAs", Compound Semiconductor, vol. 2, no. 5, pp. 26-32, 1996. PA1 [15] K. G. Merkel, C. L. A. Cerny, V. M. Bright, F. L. Schuermeyer, T. P. Monahan, R. T. Lareau, R. Kaspi, and A. K. Rai, "Improved p-channel InAlAs/GaAsSb HIGFET Using Ti/Pt/Au Ohmic Contacts to Beryllium Implanted GaAsSb", Solid State Electronics, vol. 39, pp. 179-191, 1996. PA1 [16] K. J. Chen, T. Enoki, K. Maezawa, K. Arai, and M. Yamatoto, "High-Performance InP-Based Enhancement-Mode HEMT's Using Non-Alloyed Ohmic Contacts and Pt-Based Buried-Gate Technologies", IEEE Trans. on Elect. Dev., vol. 43, no. 2, pp. 252-257, February, 1996. PA1 [17] J. M. Woodall et al., "Ohmic Contacts to n-GaAs Using Graded Band Gap Layers of Ga.sub.1-x In.sub.x As Grown by Molecular Beam Epitaxy" J. Vacuum Science Technology. Vol 19, number 3, September/October 1981, pp 626. PA1 [18] S. Kuroda et al. "HEMT with Non-alloyed Ohmic Contacts Using n.sup.+ -InGaAs Cap Layer", IEEE Electron Device Letters, Volume EDL-8, number 9, September 1987, pp 389. PA1 [19] C. K. Peng et al. ,"Extremely Low Non-alloyed and Alloyed Contact Resistance Using an InAs Cap Layer on InGaAs by Molecular-Beam Epitaxy", J. Applied Physics Volume 64, number 1, Jul. 1, 1988, pp 429. PA1 [20] T. Nittono et al., "Non-Alloyed Ohmic Contacts to n-GaAs Using Compositional Graded In.sub.x Ga.sub.1-x As Layers", Japanese Journal of Applied Physics, Volume 27, number 9, September 1988, pp 1718-1722. PA1 [21] A. Ketterson et al., "Extremely Low Contact Resistances for AlGaAs/GaAs Modulation-Doped Field-Effect Transistor Structures", J. Applied Physics. Volume 57, number 6, pp 2305. PA1 [22] J. Sewell, C. Bozada, "A Combined Electron Beam/Optical Lithography Process Step for the Fabrication of Sub-Half Micron-Gate-Length MMIC Chips", Fourth National Technology Transfer Conference, National Aeronautics and Space Administration, Publication Number 3249, 1993, pp54-59. PA1 [23] R. Zuleeg, J. Notthoff, G. Troeger "Double-Implanted GaAs Complementary JFET's", Institute of Electrical and Electronic Engineers Electron Devices Letters, Volume EDL-5, Number 1, January, 1984, pp21-23; IEEEe 0741-3106/84/0100-0021$01.00. PA1 a plurality of undoped periodic table group III-V semiconductor material layers received on a wafer substrate member; PA1 a masking inorganic dielectric material layer covering an outermost of said semiconductor material layers and having selected mask apertures therein; PA1 said masking inorganic dielectric material layer-covered semiconductor material layers including a buried, charge carrier-communicating, field-effect transistor channel layer; PA1 a p-channel transistor gate window aperture through at least one semiconductor layer covering said channel layer, said p-channel gate window aperture being in registration with one of said masking inorganic dielectric material layer mask apertures; PA1 a p-channel transistor Schottky barrier gate element received in charge carrier flow-controlling proximity of said channel layer in said p-channel transistor gate window aperture; PA1 p-channel transistor source and drain current conductor elements located on charge carrier flow upstream and downstream sides of said p-channel gate window aperture and each comprising aligned stacks of locally doped successive layer semiconductor material extending between conductor ends at said outermost semiconductor material layer and at said channel layer; PA1 p-channel transistor source and drain ohmic contact elements received on said outermost semiconductor material layer each in registration with other non-gate of said mask apertures and in electrical connection therein with one of said p-channel current conductor outermost semiconductor material layer stack ends; PA1 a n-channel transistor gate window aperture through at least one semiconductor layer covering said channel layer, said n-channel gate window aperture being in registration with one of said masking inorganic dielectric material layer mask apertures; PA1 a n-channel transistor Schottky barrier gate element received in charge carrier flow-controlling proximity of said channel layer in said n-channel transistor gate window aperture; PA1 n-channel transistor source and drain current conductor elements located on charge carrier flow upstream and downstream sides of said n-channel gate window aperture and each comprising aligned stacks of locally doped successive layer semiconductor material extending between stack ends at said outermost semiconductor material layer and said channel layer; PA1 n-channel transistor source and drain ohmic contact elements received on said outermost semiconductor material layer each in registration with other non-gate of said mask apertures and in electrical connection therein with one of said n-channel current conductor outermost semiconductor material layer stack ends; PA1 said p-channel and n-channel gate elements and said p-channel and n-channel source and drain ohmic contact elements all being comprised of a same metallic common composition.
The item 23 R. Zuleeg, J. Notthoff, G. Troeger "Double-Implanted GaAs Complementary JFET's", article in this list is of perhaps special interest with respect to a complementary pair device; however, it should be recognized that this article teaches the use of multiple metallization steps in comparison with the single metallization of the present invention.
Although each of these documents from the prior art may therefore relate to an aspect of the present invention it is believed the invention as described herein represents the first combination of the plurality of concepts and compromises necessary to achieve a successful single metal, non-alloyed contact, inorganic secondary mask-aided, radiation resistant, low power requirement and microwave-capable enhancement mode complementary field-effect transistor pair.
The above identified previously filed and commonly assigned patent application documents are also of interest with respect to the present invention in the sense that they disclose field-effect transistors of the MESFET and related types and the fabrication of these transistors using single metallization secondary mask-inclusive processing. Notably, however, the transistors of these previously filed and commonly assigned documents are of the single transistor n-channel depletion mode type wherein electron charge carriers are utilized and, moreover, these transistors are fabricated through use of diffusion dopings in layers of the transistor rather than controlled implanted dopings in initially non-doped layers as enable the present invention.